1. Field of the Invention
The invention relates to a wafer level packaging method, particularly to a wafer level packaging method for elements with fragile structure.
2. Description of the Related Art
FIGS. 1A to 1J show a conventional wafer level packaging method. Referring to FIGS. 1A to 1D, firstly, a metal layer 10 (for example, copper) having a first surface 101 and a second surface 102 is provided, and the second surface 102 corresponds to the first surface 101. Then, a plurality of caves 103 are formed on the first surface 101.
The caves 103 are formed by the following steps. Referring to FIG. 1A, a first photoresist 11 is formed on the first surface 101 and the second surface 102 respectively. Referring to FIG. 1B, a plurality of first openings 111 are formed on the first photoresist 11. The first openings 111 are formed by using exposure and development. Referring to FIG. 1C, the first surface 101 being corresponding to the first openings 111 is etched to form the caves 103. The first openings 111 corresponding to caves 103 are used for formed the caves 103. Referring to FIG. 1D, the first photoresist 11 is removed.
FIGS. 1E and 1F show that a cover 13 is formed in the cave 103 and around the cave 103. The cover 13 is formed by the following steps. Referring to FIG. 1E, a second photoresist 12 is formed on the first surface 101 and the second surface 102 respectively. The second openings 121 are formed by using exposure and development. A plurality of second openings 121 are formed on the second photoresist 12. The second openings 121 are larger than the caves 103 and respectively correspond to the caves 103. Referring to FIG. 1F, a cover 13 is formed in the cave 103 and around the cave 103. The cover 13 has a first part 131 and a second part 132. The first part 131 of the cover 13 is disposed in the cave 103. The second part 132 of the cover 13 is disposed on the first surface 101 and around the cave 103.
Referring to FIG. 1G, a wafer 14 is disposed onto the covers 13. The wafer 14 has an active surface 141, and a plurality of micro-mechanical elements 142 and separating walls 143 are disposed on the active surface 141. Each micro-mechanical element 142 is disposed in the corresponding cover 13. Each separating wall 143 is disposed on the corresponding second part 132 of the cover 13. Referring to FIG. 1H, the metal layer 10 is removed.
Referring to FIGS. 1I and 1J, they show the final process of the conventional wafer level package structure. The wafer 14 is upside-down. Utilizing a conventional bump chip carrier (BCC) process, the wafer 14 is bonded with wires 15. Finally, the wafer 14 is encapsulated with encapsulating material 16 to form a conventional wafer level package structure 1.
There are some shortcomings in the above-mentioned conventional wafer level packaging method, such as that leads of the conventional wafer level package structure 1 electrically connecting with outer elements must be formed by utilizing the conventional bump chip carrier (BCC) process. As a result, the packaging process is complicated, and the cost will increase. Moreover, the size of the conventional wafer level package structure 1 will be big.
Consequently, there is an existing need for providing a wafer level package and method for making the same to solve the above-mentioned problems.